@Porn Loader:
CODE
Winchester (90 nm SOI)
CPU-Stepping: D0
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
MMX, Extended 3DNow!, SSE, SSE2, AMD64, Cool'n'Quiet, NX Bit
Socket 939, HyperTransport (1000 MHz, HT1000)
VCore: 1.40 V
Power Consumption (TDP): 67 Watt max
First Release: 2004
Clockrate: 1800 - 2200 MHz
[edit]
Venice (90 nm SOI)
CPU-Stepping: E3
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX Bit
Socket 939, HyperTransport (1000 MHz, HT1000)
VCore: 1.35 V or 1.40 V
Power Consumption (TDP): 67 Watt max
First Release: April 4, 2005
Clockrate: 1800 - 2400 MHz
[edit]
San Diego (90 nm SOI)
CPU-Stepping: E4
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX Bit
Socket 939, HyperTransport (1000 MHz, HT1000)
VCore: 1.35 V or 1.40 V
Power Consumption (TDP): 67 Watt max
First Release: April 15, 2005
Clockrate: 2200 - 2800 MHz
Since u r a little drunker now than u were b4... i'll help u out a little.. look at the code above.... then look at the CPU-Stepping.... The CPU-Stepping is what he wants to know about... but i have never heard of a E5 revision and at that i don't think AMD would still call the revision San Diego due to that it may cause confusion 4 people...